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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Off
Figure 26: Voltage Ramp and Initialization Sequence
Ta
Tb
Tc
Td
Te
Tf
Tg
tINIT2
CK/CK#
tINIT0
Supplies
CKE
tINIT1
tINIT3
tISCKE
tINIT4
tINIT5
tZQINIT
CA
RESET
MRR
MRW
ZQ _ CAL
Valid
R TT
DQ
Note:
1. High-Z on the CA bus indicates valid NOP.
Table 8: Initialization Timing Parameters
Value
Parameter
t INIT0
t INIT1
t INIT2
t INIT3
t INIT4
t INIT5
t ZQINIT
t CKb
Min
–
100
5
200
1
–
1
18
Max
20
–
–
–
–
10
–
100
Unit
ms
ns
t CK
μ s
μ s
μ s
μ s
ns
Comment
Maximum voltage ramp time
Minimum CKE LOW time after completion of voltage ramp
Minimum stable clock before first CKE HIGH
Minimum idle time after first CKE assertion
Minimum idle time after RESET command
Maximum duration of device auto initialization
ZQ initial calibration (S4 devices only)
Clock cycle time during boot
Initialization After RESET (Without Voltage Ramp)
If the RESET command is issued before or after the power-up initialization sequence,
the reinitialization procedure must begin at Td.
Power-Off
While powering off, CKE must be held LOW ( ≤ 0.2 × V DDCA ); all other inputs must be be-
tween V ILmin and V IHmax . The device outputs remain at High-Z while CKE is held LOW.
DQ, DM, DQS, and DQS# voltage levels must be between V SSQ and V DDQ during the
power-off sequence to avoid latchup. CK, CK#, CS#, and CA input levels must be be-
tween V SSCA and V DDCA during the power-off sequence to avoid latchup.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
42
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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